[PATCH] ASoC: sgtl5000: Allow the codec to work in slave mode

[Fabio Estevam]

From: Fabio Estevam <***@freescale.com>

When configuring sgtl5000 to work in slave mode the following error is seen:

***@freescale /$ aplay dtmf_mono_16b_48000.wav
[ 11.406460] random: nonblocking pool is initialized
[ 11.600461] sgtl5000 1-000a: PLL not supported in slave mode
[ 11.609052] sgtl5000 1-000a: ASoC: can't set sgtl5000 hw params: -22
ALSA lib pcm_direct.c:980:(snd1_pcm_direct_initialize_slave) unable to install hw params
ALSA lib pcm_dmix.c:1030:(snd_pcm_dmix_open) unable to initialize slave
aplay: main:660: audio open error: Invalid argument

Do not error out when sgtl5000_set_clock() reaches the default path for slave
mode.

While at it, fix a typo in the comment.

Tested on a imx53-qsb configured as ssi in master and sgtl5000 as slave.

Signed-off-by: Fabio Estevam <***@freescale.com>
---
sound/soc/codecs/sgtl5000.c | 6 +-----
1 file changed, 1 insertion(+), 5 deletions(-)

diff --git a/sound/soc/codecs/sgtl5000.c b/sound/soc/codecs/sgtl5000.c
index a604a22..b641ed1 100644
--- a/sound/soc/codecs/sgtl5000.c
+++ b/sound/soc/codecs/sgtl5000.c
@@ -619,14 +619,10 @@ static int sgtl5000_set_clock(struct snd_soc_codec *codec, int frame_rate)
SGTL5000_MCLK_FREQ_SHIFT;
break;
default:
- /* if mclk not satisify the divider, use pll */
+ /* if mclk not satisfy the divider, use pll */
if (sgtl5000->master) {
clk_ctl |= SGTL5000_MCLK_FREQ_PLL <<
SGTL5000_MCLK_FREQ_SHIFT;
- } else {
- dev_err(codec->dev,
- "PLL not supported in slave mode\n");
- return -EINVAL;
}
}

[Mark Brown]

Post by Fabio Estevam
- /* if mclk not satisify the divider, use pll */
+ /* if mclk not satisfy the divider, use pll */
if (sgtl5000->master) {
clk_ctl |= SGTL5000_MCLK_FREQ_PLL <<
SGTL5000_MCLK_FREQ_SHIFT;
- } else {
- dev_err(codec->dev,
- "PLL not supported in slave mode\n");
- return -EINVAL;
}
}

Are you sure that the configuration that results is valid? Typically
the requirements for MCLK to other clock ratios are very similar for
master and slave modes, it's just that it tends to be a lot more obvious
when things go wrong in master mode since directly visible clocks tend
to go wrong as opposed to performance problems. Are the dividers that
we can't get configuration for purely for generating BCLK/LRCLK in
master mode or are they for other things?

[Fabio Estevam]

Hi Mark,

Post by Mark Brown

- /* if mclk not satisify the divider, use pll */
+ /* if mclk not satisfy the divider, use pll */
if (sgtl5000->master) {
clk_ctl |= SGTL5000_MCLK_FREQ_PLL <<
SGTL5000_MCLK_FREQ_SHIFT;
- } else {
- dev_err(codec->dev,
- "PLL not supported in slave mode\n");
- return -EINVAL;
}
}

Are you sure that the configuration that results is valid? Typically
the requirements for MCLK to other clock ratios are very similar for
master and slave modes, it's just that it tends to be a lot more obvious
when things go wrong in master mode since directly visible clocks tend
to go wrong as opposed to performance problems. Are the dividers that
we can't get configuration for purely for generating BCLK/LRCLK in
master mode or are they for other things?

Tested sgtl5000 slave mode with different sampling rates and it plays well.

Any particular register I should monitor?

Sorry, but I guess I did not understand your last question.

[Mark Brown]

Post by Fabio Estevam

Post by Mark Brown
Are you sure that the configuration that results is valid? Typically
the requirements for MCLK to other clock ratios are very similar for
master and slave modes, it's just that it tends to be a lot more obvious
when things go wrong in master mode since directly visible clocks tend
to go wrong as opposed to performance problems. Are the dividers that
we can't get configuration for purely for generating BCLK/LRCLK in
master mode or are they for other things?

Tested sgtl5000 slave mode with different sampling rates and it plays well.
Any particular register I should monitor?

Did you just listen or did you measure the performance?

Post by Fabio Estevam
Sorry, but I guess I did not understand your last question.

I'm really not sure how to simplify it... clearly we're skipping some
configuration here, what does it do - is it purely for generating BCLK
and LRCLK?

[Michael Trimarchi]

Hi Mark

Post by Mark Brown

Post by Fabio Estevam

Post by Mark Brown
Are you sure that the configuration that results is valid? Typically
the requirements for MCLK to other clock ratios are very similar for
master and slave modes, it's just that it tends to be a lot more obvious
when things go wrong in master mode since directly visible clocks tend
to go wrong as opposed to performance problems. Are the dividers that
we can't get configuration for purely for generating BCLK/LRCLK in
master mode or are they for other things?

Tested sgtl5000 slave mode with different sampling rates and it plays well.
Any particular register I should monitor?

Did you just listen or did you measure the performance?

Post by Fabio Estevam
Sorry, but I guess I did not understand your last question.

I'm really not sure how to simplify it... clearly we're skipping some
configuration here, what does it do - is it purely for generating BCLK
and LRCLK?

Are you talking about clock_in and sigma-delta? So no the bclk and lrclk but
the clkin of the codec.

Michael

Post by Mark Brown
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[Mark Brown]

Post by Michael Trimarchi

Post by Mark Brown

Post by Fabio Estevam
Any particular register I should monitor?

Did you just listen or did you measure the performance?

Post by Fabio Estevam
Sorry, but I guess I did not understand your last question.

I'm really not sure how to simplify it... clearly we're skipping some
configuration here, what does it do - is it purely for generating BCLK
and LRCLK?

Are you talking about clock_in and sigma-delta? So no the bclk and lrclk but
the clkin of the codec.

I'm sorry but I can't parse what you're saying terribly clearly - please
bear in mind that I don't know anything about this device, that's one of
the reasons I'm having to ask questions here. If the configuration that
is being skipped is not about generating BCLK and LRCLK then it seems
like it's going to be wanted in slave mode as well as master.

[Fabio Estevam]

Hi Mark,

Post by Mark Brown

Post by Michael Trimarchi

Post by Mark Brown

Post by Fabio Estevam
Any particular register I should monitor?

Did you just listen or did you measure the performance?

Post by Fabio Estevam
Sorry, but I guess I did not understand your last question.

I'm really not sure how to simplify it... clearly we're skipping some
configuration here, what does it do - is it purely for generating BCLK
and LRCLK?

Are you talking about clock_in and sigma-delta? So no the bclk and lrclk but
the clkin of the codec.

I'm sorry but I can't parse what you're saying terribly clearly - please
bear in mind that I don't know anything about this device, that's one of
the reasons I'm having to ask questions here. If the configuration that
is being skipped is not about generating BCLK and LRCLK then it seems
like it's going to be wanted in slave mode as well as master.

This patch does not skip any configuration. It just remove the error
case for sgtl5000 in slave mode.

Not sure why the error case was there in the first place, as I think
sgtl5000 slave mode has never been tested before.

[Mark Brown]

Post by Fabio Estevam

Post by Mark Brown
I'm sorry but I can't parse what you're saying terribly clearly - please
bear in mind that I don't know anything about this device, that's one of
the reasons I'm having to ask questions here. If the configuration that
is being skipped is not about generating BCLK and LRCLK then it seems
like it's going to be wanted in slave mode as well as master.

This patch does not skip any configuration. It just remove the error
case for sgtl5000 in slave mode.
Not sure why the error case was there in the first place, as I think
sgtl5000 slave mode has never been tested before.

The comment says "if mclk not satisfy the divider, use pll" and then
does in fact skip configuring the PLL (or at least a register change
which looks like it does that). Looking at the code it seems like
there's a requirement for MCLK to be one of the standard multiples of
the sample rate.

[Fabio Estevam]

Post by Mark Brown
The comment says "if mclk not satisfy the divider, use pll" and then
does in fact skip configuring the PLL (or at least a register change
which looks like it does that). Looking at the code it seems like
there's a requirement for MCLK to be one of the standard multiples of
the sample rate.

Ok, got it now.

For sgtl5000 to operate in slave mode it can only work in "Synchronous
SYS_MCLK input" mode.

In this mode only the following rates can be supported: 256*Fs, 384*Fs, 512*Fs.

On the board I was testing this I was getting a ratio of 233, so the
original code returned -EINVAL.

So the current behaviour looks correct.

We could improve the 'PLL not supported in slave mode' error message
though putting the actual ratio we got.

Will send a patch for this shortly.